Ring style power gating involves placing a ring of power gate transistors typically around the periphery of an integrated circuit block, e.g., a microprocessor core, and directing or funneling the VSS or VDD current through the ring of transistors, from a power supply. See S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, “1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS,” IEEE J. Solid-State Circuits 30, No. 8, pp. 847-854, August 1995, which is incorporated herein in its entirety by reference.
In some applications, a maximum current throughput is a limiting design or performance parameter. In particular, a problem exists in high frequency processors where current crowds at the power gate ring border and exceeds the current limits of the C4 electrical contact bumps connected to one or both sides of the power gate ring.
One proposed solution to this problem is to limit the maximum current of the circuit block that is power gated. However, this will limit the performance of the circuit block and will limit the regions where ring style power gating can be used.
Alternatively, integrated power gating can be used to distribute the power gates throughout the integrated circuit block being gated. Such distributed power gating, however, adds design complexity, which can require significant additional design time for a CPU core.
Accordingly, improvements are sought in ring power gating.